| Autor: |
Mu-Chun Wang, Wen-Shiang Liao, Wei Chao-Nan, Tien-Szu Shen, Bor Hui-Yun, Wen-How Lan |
| Rok vydání: |
2019 |
| Předmět: |
|
| Zdroj: |
2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA). |
| DOI: |
10.1109/ipfa47161.2019.8984910 |
| Popis: |
Through the electrical measurement plus the heat stress to enhance the existed or latent defects of FinFETs in the nano-node process flow is a useful metrology. This method not only effectively and timely provides the mapping analysis in a whole wafer, but the sensed data may be correlated to the process variation and optimization in statistical analysis. Besides the common electrical characteristics in ON/OFF current, the punch-through and drain-induced barrier lowering (DIBL) effects like a pair of detectors are good tools to probe the channel integrity. More process parameters of VT implantation related to these two effects are discussed. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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