| Autor: |
Hong-June Park, Jae-Yoon Sim, Jin-Ho Seo, Hwanseok Yeo, Jun-Hyun Bae, Jae-Whui Kim |
| Rok vydání: |
2007 |
| Předmět: |
|
| Zdroj: |
CICC |
| DOI: |
10.1109/cicc.2007.4405755 |
| Popis: |
An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a small delay and the fixed rising-edge property for loop-embedding. The chip fabricated with a 0.13 um CMOS process gives the DLL data rate of 667 Mbps~1.6 Gbps and the output duty cycle of 47.8%~49% for the input duty cycle of 23%~76%, at 1.6 Gbps and 1.2 V. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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