| Autor: |
KangDuck Lee, Daehyun Jang, Joong-Won Jeon, Woon-Hyuk Choi, Joo-Hyun Park, No-Young Chung, Ki-Su Kim, Kun Young Chung, Seung Weon Paek, Bong-Seok Kim, DongSup Song, Byung-Moo Kim, WooYoung Noh, Sang-Min Bae, HyunSeok Song, Kee Sup Kim, Dae-Wook Kim, Jae Hyun Kang, Hungbok Choi, Seong-Ho Park, Junsu Jeon, Kyu-Myung Choi, Young-Duck Kim, Sung-eun Yu, Jinwoo Lee, Naya Ha, Young-ki Hong |
| Rok vydání: |
2012 |
| Předmět: |
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| Zdroj: |
Design for Manufacturability through Design-Process Integration VI. |
| ISSN: |
0277-786X |
| DOI: |
10.1117/12.920029 |
| Popis: |
A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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