3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling

Autor:	W. Rachmady, Phan Anh, G. Dewey, P. Nguyen, Matthew V. Metz, Tung I-Cheng, Patrick Morrow, Rajat Kanti Paul, Scott B. Clendenning, Nicole K. Thomas, A. A. Oni, Ryan Keech, Marko Radosavljevic, Huang Cheng-Ying, Alaan Urusa, Manan Mehta, Kang Jun Sung, A. Lilak, Mannebach Ehren, Hui Jae Yoo, Bob Turkot, Kabir Nafees, S. Vishwanath, K. L. Cheong, Richard E. Schenker, B. Krist, Michael K. Harper, Jack Portland Kavalieros
Rok vydání:	2020
Předmět:	Moore's law Materials science business.industry media_common.quotation_subject Transistor Hardware_PERFORMANCEANDRELIABILITY law.invention PMOS logic CMOS law Logic gate Hardware_INTEGRATEDCIRCUITS Inverter Optoelectronics business Metal gate NMOS logic Hardware_LOGICDESIGN media_common
Zdroj:	2020 IEEE International Electron Devices Meeting (IEDM).
Popis:	We demonstrate 3-D self-aligned stacked NMOS-on-PMOS multiple Si nanoribbon transistors with successful integration of vertically stacked dual source/drain EPI process and vertically stacked dual metal gate process. Both top NMOS and bottom PMOS show high on-state performance and superior short channel control. A functional CMOS inverter is also demonstrated with well-balanced voltage transfer characteristics. The 3-D self-aligned stacked CMOS nanoribbon transistor is demonstrated as a promising transistor architecture to continue Moore’s law scaling.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::df2fecb4c1020f6a74997a8120152a6c https://doi.org/10.1109/iedm13553.2020.9372066 Zobrazit plný text záznamu