A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

Autor:	Wei-Hsing Huang, Ren-Shuo Liu, Yung-Ning Tu, Shimeng Yu, Yen-Cheng Chiu, Meng-Fan Chang, Qiang Li, Xiaoyu Sun, Jia-Jing Chen, Jing-Hong Wang, Rui Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Wei-Chen Wei, Xin Si, Ssu-Yen Wu
Rok vydání:	2020
Předmět:	Computer science business.industry Overhead (computing) Enhanced Data Rates for GSM Evolution Static random-access memory Electrical and Electronic Engineering business Chip Voltage reference Computer hardware
Zdroj:	IEEE Journal of Solid-State Circuits. 55:189-202
ISSN:	1558-173X 0018-9200
Popis:	Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even–odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two’s complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global–local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 $\times $ 60 b T8T unit-macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5–45.36 TOPS/W under 5-b MACV output.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::de6d636f7ec83afda423834139c7f52c https://doi.org/10.1109/jssc.2019.2952773 Zobrazit plný text záznamu