A Stacked Embedded DRAM Array for LPDDR4/4X using Hybrid Bonding 3D Integration with 34GB/s/1Gb 0.88pJ/b Logic-to-Memory Interface

Autor: Zhan Qiong, Wang Kexin, Tan Jie, Wang Zhengwen, Li Jin, Ren Qiwei, Cheichan Kau, L. V. Hangbing, Wang Chunjuan, Sun Peng, Ching-Sung Ho, David Yang, Duan Huifu, Wang Song, Li Hua, Sun Hongbin, Kang Yi, Long Xiaodong, Wang Fan, Yu Guoqing, Jia Xuerong, Yu Bing, Yang Daohong, Li Qiannan, Fu Ni, Zhou Jun, Zuo Fengguo, Liu Ming, Jiang Xiping, Bai Liang, Li Mei, Bai Fujun, Hu Sheng
Rok vydání: 2020
Předmět:
Zdroj: 2020 IEEE International Electron Devices Meeting (IEDM).
DOI: 10.1109/iedm13553.2020.9372039
Popis: Increasing demand for DRAM scaling and high-bandwidth has driven DRAM technology to 3D/2.5D integration. With the innovative Hybrid Bonding technology, a new Stacked Embedded DRAM (SEDRAM) architecture was developed on LPDDR4/4X product. In this SEDRAM, a DRAM array wafer and logic wafer were fabricated separately and then face-to-face fusion connected through ultra-high-density, low-resistance Hybrid Bonding. By separating the control, I/O, DFT and periphery circuits to a logic die, SEDRAM offers a novel approach to DRAM product development and accomplishes an extremely high-bandwidth logic-to-memory interface speed of 34GBps per 1Gb with low power consumption as low as 0.88pJ/bit.
Databáze: OpenAIRE