A Modified Variable Step Size for Fractional Least Mean Square Algorithm for System Identification and Its FPGA Implementation
| Autor: | Yash Keju Barapatre, Sarita Nanda, Ansuman Patnaik |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Least mean square algorithm
021110 strategic defence & security studies Steady state (electronics) Computer science 0211 other engineering and technologies System identification 02 engineering and technology Least mean squares filter Variable (computer science) Convergence (routing) MATLAB Field-programmable gate array computer Algorithm computer.programming_language |
| Zdroj: | 2020 International Conference on Communication and Signal Processing (ICCSP). |
| DOI: | 10.1109/iccsp48568.2020.9182145 |
| Popis: | In this paper, a variable step-size fractional least mean square (FLMS) named as modified variable step-size FLMS (MVSS-FLMS) is proposed to address the issue of faster convergence time and lower steady state error of the FLMS algorithm. In order to test the superiority of the algorithm, the algorithm is verified using MATLAB and Verilog code is written and implemented on FPGA. Matlab simulations shows that the proposed algorithm achieves faster convergence and lower runtime compared to the existing FLMS and robust VSSFLMS (RVSS-FLMS). |
| Databáze: | OpenAIRE |
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