A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding

Autor: H. Yoshikawa, Mitsuo Soneda, Mitsuharu Ohki, Katsunori Seno, Y. Fukuzawa, M. Aikawa, E. Iwata, Seiichiro Iwase, K. Nishibori, T. Yamazaki, H. Hanaki, Y. Kondo, Ichiro Kumata, K. Hasegawa, H. Takamuki, Hiroshi Okuda, T. Nagai
Rok vydání: 2002
Předmět:
Zdroj: 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
DOI: 10.1109/isscc.1997.585378
Popis: In multimedia applications, various video encoding/decoding standards such as MPEG2, MPEG1 and emerging algorithms call for a DSP solution of the extremely computation-intensive tasks. Several DSPs have been developed based on intensive pipeline processing at the macro-block level. In these DSPs, macroblock-based pipeline memory slices are needed for each pipeline stage. Programmability is limited by the hard-wired macros to be incorporated such as DCT and Quantizer. A microprocessor or a media-processor with multimedia-enhanced instructions has not yet been applied to MPEG2 encoding. This DSP for real-time codec applications has the following features: (a) extensive use of data parallelism inside the macro-block data structure, (b) flexible data path for coding algorithms to enhance gate utilization and to reduce the use of macro-block pipeline memory, (c) data path design suitable for (but not limited to) fast DCT/IDCT algorithms.
Databáze: OpenAIRE