Low-Level VHDL Modeling of Digital-to-Analog Converter

Autor:	Daniel Teng, R.J. Bolton, Peng Huang
Rok vydání:	2007
Předmět:	Computer science law business.industry Embedded system VHDL Hardware description language Digital-to-analog converter Hardware design languages business computer computer.programming_language law.invention
Zdroj:	2007 Canadian Conference on Electrical and Computer Engineering.
DOI:	10.1109/ccece.2007.28
Popis:	This paper describes an approach to low-level VHDL modeling of digital-to-analog converter (DAC). A 12-bit DAC was modeled and simulated with Cadence NC-Sim simulator to test the feasibility of the approach. The simulation result shows that the approach can achieve faster simulation than circuit simulations with better accuracy than behavioral simulations.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::ddf3d9f31e5e1c49c21bf778c9505d5e https://doi.org/10.1109/ccece.2007.28 Zobrazit plný text záznamu