Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools
| Autor: | Guerric de Streel, David Bol, Francois Stas |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Engineering Analogue electronics business.industry 02 engineering and technology 01 natural sciences Integrated circuit layout 020202 computer hardware & architecture Design layout record 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Netlist Electronic engineering Place and route Routing (electronic design automation) Layout Versus Schematic business IC layout editor |
| Zdroj: | NEWCAS |
| DOI: | 10.1109/newcas.2016.7604758 |
| Popis: | The design of analog blocks is a bottleneck in a mixed-signal system designs due to the time-consuming layout step needing human intervention at each iteration of the optimization phase. In this paper, we propose a global automatic sizing and layout integrated methodology for analog block sizing including post-layout verification. The proposed optimizer is based on commercial digital place and route tools for the layout step and does not require custom layout procedures or dedicated layout-template framework. An analog cell library in LEF format with transistor, resistance and capacitance layout is used by the PnR tool allowing placement and routing of these elements. A post-layout netlist with parasitic resistances and capacitances as well as proximity effects is then extracted from generated the GDS file for post-layout simulation. A genetic algorithm is implemented as an optimization kernel allowing automatic sizing iteration. The optimizer is demonstrated in an advanced 28nm FDSOI process on typical analog blocks (two-stage basic amplifier, low-noise amplifier, ΔV T voltage reference and digital-controller oscillator). |
| Databáze: | OpenAIRE |
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