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Mapping is the off-line allocation of the tasks that represent a parallelised algorithm across a multiprocessor architecture. In this paper the target architecture is heterogeneous, where a number of computationaly disparate processors are integrated within a single network. This paper describes three mapping approaches that attempt to minimise the cycle time of several parallelised algorithms. The mapping algorithms have been embedded into a suite of design tools that allow a rapid translation from an application algorithm to a parallel implementation. These tools are used to explore the efficacy of the mapping algorithms. A simple heuristic is appraised first, followed by an examination of a genetic algorithm (GA) approach. Initially, the GA utilises a simple parallel architecture model. However, this leads to the embedding of the target hardware within the objective function to improve performance. Finally, the effectiveness of these approaches are examined and contrasted. |
