| Autor: |
Brian L. F. Daku, M.A. Bree, R.J. Bolton, David E. Dodds, S. Kumar |
| Rok vydání: |
1992 |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits. 27:184-190 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/4.127341 |
| Popis: |
A node-parallel Viterbi decoding architecture and bit-serial processing and communication are presented. An important aspect of this structure is that short-constraint-length decoders may be interconnected, without loss of throughput, to implement a Viterbi decoder of larger constraint length. The convolutional encoder trellis is modeled by appropriate wiring of decoder processing nodes: a variety of generating codes can be accommodated. Bit-serial communication links between nodes require only a single wire each and thus interconnection area is relatively small. During each decoding cycle, more than 50 b need to be communicated on each serial link and thus the technique is limited to moderate bit rate applications. A constraint length K=4 'proof of concept' chip was developed using 9860 transistors in 3 mu m CMOS on a 4.51-mm*4.51-mm die size. The complete circuit operates at 280 kb/s and supports any rate 1/2 or 1/3 code with eight-level soft decision. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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