Quasi-Static Terminal-Charge Model for Symmetric Double-Gate Ferroelectric FETs
| Autor: | Mulaka Haranadha Reddy, Srivatsava Jandhyala |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Engineering business.industry Transistor Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Capacitance Electronic Optical and Magnetic Materials Numerical integration law.invention Terminal (electronics) law Logic gate 0103 physical sciences Limit (music) Hardware_INTEGRATEDCIRCUITS Electronic engineering Field-effect transistor Electrical and Electronic Engineering 0210 nano-technology business Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | IEEE Transactions on Electron Devices. 63:940-945 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2016.2519761 |
| Popis: | Symmetric double-gate ferroelectric FETs (SDG-FeFETs) have better short-channel electrical behavior and hold promise in reducing the subthreshold swing below the classical Boltzmann’s limit. Surface potential and drain current models for SDG-FeFETs have already been published in the literature. In this paper, we derive the quasi-static terminal-charge models for these devices, which can be seamlessly integrated into standard circuit simulators using the Verilog-A interface. The terminal-charge models proposed are shown to match very well with exact numerical integration of Ward–Dutton terminal-charge integrals, for all bias conditions. Core compact model for the SDG-FeFET is implemented in a SPICE circuit simulator, and the simulation of different circuits built using SDG-FeFET transistors shows improvement in their switching behavior. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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