Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System
Autor: | Jose L Nunez-Yanez, Mohammad Hosseinabady |
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Rok vydání: | 2020 |
Předmět: |
050101 languages & linguistics
Multi-core processor Computer science business.industry 05 social sciences Embedded intelligence 02 engineering and technology MPSoC Convolutional neural network High-level synthesis Embedded system 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing 0501 psychology and cognitive sciences Multiplication business Field-programmable gate array Sparse matrix |
Zdroj: | PARMA-DITAM@HiPEAC |
DOI: | 10.1145/3381427.3381428 |
Popis: | Embedded intelligence is becoming the primary driver for new applications in industry, healthcare, and automotive, to name a few. The main characteristics of these applications are high computational demand, real-time interaction with the environment, security, low power consumption, and local autonomy, among others. Addressing these diverse characteristics, researchers have proposed heterogeneous multicore embedded systems comprising CPUs, GPUs, FPGAs, and ASICs. Whereas each computing element provides a unique capability to enable one of the application characteristics, collaborating these processing cores in running an application to get the maximum performance is a crucial challenge. This paper considers the collaborative usage of a multicore CPU and an FPGA in a heterogeneous embedded system to improve the performance of sparse matrix operations, which have been essential techniques in reducing the inference complexity in machine learning techniques, especially deep convolutional neural networks. Experimental results show that the collaborative execution of sparse-matrix-dense-matrix multiplication on the Xilinx Zynq MPSoC, a heterogeneous CPU+FPGA embedded system, can improve the performance by a factor of up to 42% compared with just using the FPGA as an accelerator. |
Databáze: | OpenAIRE |
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