Exploiting regularity: breakthroughs in sub-7nm place-and-route
| Autor: | Xuelian Zhu, Lars W. Liebmann, Paul Gutwin, Jan Petykiewicz, Vassilios Gerousis |
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| Rok vydání: | 2017 |
| Předmět: |
Interconnection
Computer science business.industry 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences 010309 optics Reduction (complexity) Semiconductor 0103 physical sciences Electronic engineering Node (circuits) Place and route Physical design 0210 nano-technology Power network design business |
| Zdroj: | SPIE Proceedings. |
| ISSN: | 0277-786X |
| DOI: | 10.1117/12.2259981 |
| Popis: | As pitch scaling is becoming constrained not only by lithographic resolution limits but alos by fundamental device and interconnect challenges the semiconductor industry has turned to cell-height reduction as a means of achieving competitive area scaling. The risk in using cell-height reduction to compensate for insufficient pitch scaling is that place- and-route inefficiencies caused by wiring congestion at the block level of the design can easily eliminate any area scaling gains made at the cell level of the design. This paper shows how careful cell-architecture optimization, physical design methodology changes, and place-and-route innovations have led to competitive block level area scaling for 7nm technology nodes and beyond. Data is presented to show that an entire node’s worth of scaling can be achieved through these comprehensive design-technology co-optimization efforts. |
| Databáze: | OpenAIRE |
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