| Popis: |
Multi-patterning, like LE and SAMP, has been in production for several years. It is expected to remain a standard in patterning, even in the case where industry adopts EUV photo lithography. As scaling continues, the precision of pattern placement remains challenging. Edge Placement Error (EPE) has been proposed to define the requirements of a patterning process. Many authors have created statistical models for EPE, and gathered statistical data for CD and overlay (OVL), to make predictions about future technology specifications1-5. This work makes the following contributions: Emphasis on large amount (63K) of on-product measurements Use of ANOVA table to assess the hypothesis that a contender process is better than a POR process To differentiate our work, we have used the stochastic variable IPFE (Interactive Pattern Fidelity Error), which is an indicator to quantify the quality of on-wafer edge placement accuracies in multi-patterning6. In our previous paper, we have studied how overlay, LCDU and pitch walk factor into the IPFE budget7. In this work, we focus on experimental verification of the expected relationships between LCDU, overlay and CD variation, applied to the case of SADP (block on spacer): We re-confirm that population ‘blocks-on-gap’ have a worse IPFE performance than ‘block-on-core’ We determine experimental behavior of IPFE vs line CD, block CD, and overlay (w/o assumption for any model) From this exercise, we can conclude that this IPFE indicator is a robust metric for the managing quality of any integrated patterning scheme. |
