A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS
| Autor: | Jong-Kee Kwon, Young Kyun Cho, Kuk-Tae Hong, Young-Deuk Jeon, Kwi-Dong Kim, Jae-Won Nam, Woo-Yol Lee |
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| Rok vydání: | 2010 |
| Předmět: |
Engineering
Spurious-free dynamic range Settling time business.industry Analog-to-digital converter Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY law.invention Capacitor CMOS law Hardware_INTEGRATEDCIRCUITS Electronic engineering Operational amplifier Hardware_ARITHMETICANDLOGICSTRUCTURES business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Shift register |
| Zdroj: | CICC |
| DOI: | 10.1109/cicc.2010.5617457 |
| Popis: | This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification time of a residue opamp. To reduce power and area, the opamp is shared between two channels. A reference buffer with a deglitch circuit reduces the glitch and settling time of reference voltages. The prototype ADC fabricated in a 65nm CMOS process shows a SNDR of 55.2dB and a SFDR of 63.5dB with a 2.4MHz input at 204MS/s. The ADC occupies 0.22mm2 and dissipates 9.15mW at a 1.0V supply. The FoM of the ADC is 95.4fJ/conversion-step. |
| Databáze: | OpenAIRE |
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