| Autor: |
Raghavasimhan Sreenivasan, H. He, James Chingwei Li, T. Levin, Shogo Mochizuki, Ali Khakifirooz, Bruce B. Doris, Darsen D. Lu, Dechao Guo, Pouya Hashemi, Huiming Bu, Benjamen N. Taber, Gen Tsutsui, Frederic Allibert, Bich-Yen Nguyen, S. M. Mignot, Theodorus E. Standaert, Tenko Yamashita, Winston Chern, Alexander Reznicek, C-Y Chen, T-S King Liu, K. Rim, Kangguo Cheng, E. C. Wall, Yunpeng Yin, Nuo Xu, Nicolas Loubet, Veeraraghavan S. Basker, Pierre Morin |
| Rok vydání: |
2013 |
| Předmět: |
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| Zdroj: |
2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). |
| DOI: |
10.1109/s3s.2013.6716520 |
| Popis: |
Strain engineering has been in the heart of CMOS technology for over a decade. However, the effectiveness of conventional strain elements, such as stress liners, embedded S/D stressors, and stress memorization, is significantly reduced when device gate pitch is scaled below 100 nm as needed for 14nm node and beyond. Substrate strain engineering, where the channel itself is formed out of a strained semiconductor, e.g. in the form of strained silicon directly on insulator (SSDOI) or strained SiGe-on-insulator has the advantage that the strain is independent of the device pitch or gate length as long as the active region is made sufficiently long and the strain is maintained throughout the device processing. We have already shown that in a FinFET structure the starting biaxial strain in the SSDOI substrate is converted to a more beneficial uniaxial strain, strain can be maintained throughout typical thermal processing, and demonstrated roughly 15% increase in NFET performance in deeply scaled FinFETs. However, this is still far less than the performance gain we reported recently in ETSOI devices. In this work, for the first time we report NFET performance gain in SSDOI FinFETs fabricated with contacted gate pitch (CGP) down to 64nm. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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