Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL
| Autor: | Yuka Onizuka, Yudong Zhang, Zhaowen Wang, Peter R. Kinget |
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| Rok vydání: | 2022 |
| Předmět: | |
| Zdroj: | IEEE Journal of Solid-State Circuits. 57:1776-1787 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | We present a high-accuracy, low-jitter, multi-phase clock generator (MPCG) based on a multi-phase, injection-locked ring oscillator (MPIL-ROSC) with a quadrature delay-locked loop (QDLL). The QDLL tunes the ring oscillator (ROSC) self-oscillation frequency ( $f_{{0}}$ ) and provides it with multi-phase injection signals. The proposed architecture breaks the intrinsic tradeoff between jitter and phase accuracy in two-phase injection-locked ROSCs. The MPCG's eight-phase output clock drives a 7-bit phase interpolator (PI) for phase and frequency deskew. A 1.2-V 65-nm CMOS MPCG prototype chip has a better-than-1° eight-phase accuracy and 58.8 ${fs}_{{rms}}$ jitter (integrated from 100 kHz to 1 GHz), while consuming 15.6 mW at 7 GHz, yielding a -252.7-dB figure of merit ( ${FOM}_{{jitter}}$ ). The peak-to-peak integral nonlinearity (INL) and the peak-to-peak differential nonlinearity (DNL) of the PI are less than 1.9 and 1.2 LSB, respectively, across a frequency range from 5 to 8 GHz. |
| Databáze: | OpenAIRE |
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