A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation
| Autor: | Mahmoud Meribout, Samir Teniou |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Digital signal processor
Computer science Pipeline (computing) Clock rate 02 engineering and technology Dielectric Parallel computing Electrical capacitance tomography 01 natural sciences Capacitance Computational science Computer Science::Hardware Architecture Gate array 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering Field-programmable gate array Hardware architecture 020208 electrical & electronic engineering 010401 analytical chemistry IEEE floating point 0104 chemical sciences Parallel processing (DSP implementation) Hardware and Architecture Distributed memory Software AND gate |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:1320-1328 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2016.2636184 |
| Popis: | This paper presents a new hardware algorithm for real-time and nonlinear 2-D electrical capacitance tomography (ECT) imaging, along with its parallel hardware architecture. A potential application of this system is to reconstruct in real time cross-sectional image of a two-phase fluid with different dielectric constants when it passes through a given section of a pipeline. The proposed hardware algorithm explores the spatial correlation that may occur between one or several consecutive frames. It uses this property to reformulate the classical regularized forward and inverse problems that are indeed very time consuming, preventing them to be used for fast ECT applications. As a result, the proposed algorithm features one-single-step iteration with a substantial reduction of the size of the Jacobian matrix. In addition, the intrinsically parallel feature of the algorithm makes it suitable for parallel hardware architecture. This architecture is based on a pipeline multiprocessor architecture using advanced features of field-programmable gate array technology. It explores the variable bit-width and floating-point multipliers array available in the digital signal processor blocks, to cooperatively perform the partial matrix product with associated arithmetic and logic units, and distributed memory. The experimental results obtained on a two-phase flow loop demonstrate the capability of the system to build in real time and with good accuracy (e.g., less than 3% error) the cross-sectional image of the fluid passing through the pipeline. Around 560 frames of 4096 moving boundary pixels can be reconstructed in 1 s using IEEE754 floating-point data representation and a clock frequency of 400 MHz, for a total power consumption of less than 33 W. |
| Databáze: | OpenAIRE |
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