An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel® Xeon® Processor E5 Family

Autor:	Ramesh Arvapalli, Moty Mehalel, Songnian He, Min Huang
Rok vydání:	2013
Předmět:	Engineering Xeon business.industry CPU cache Pipeline burst cache Integrated circuit design Parallel computing Modular design Redundancy (engineering) Electrical and Electronic Engineering business Electrical efficiency Computer hardware Efficient energy use
Zdroj:	IEEE Journal of Solid-State Circuits. 48:1954-1962
ISSN:	1558-173X 0018-9200
DOI:	10.1109/jssc.2013.2258815
Popis:	An energy efficient on-die 20-way set associative L3 cache of size 20 MB for the Intel® Xeon® processor E5 family is presented. It is manufactured in the Intel's 32-nm second generation of high-K dielectric metal gate process with 9-copper metal layers. The L3 cache design uses 0.2119 um 2 cell for the high density big array and 0.2725 um 2cell for the high performance smaller arrays. The power efficiency was achieved by employing advanced power saving schemes and effective Vccmin design techniques. The proposed L3 cache topology seamlessly supports a high density modular and energy efficient designs. The effective and rich redundancy design improves both yield and low voltage operations. The L3 cache achieves more than 20-40% energy efficiency when compared to previous generations and demonstrates wide operating ranges from 1.2 GHz at below 0.7 V to greater than 4.0 GHz at above 1.0 V.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::db383bae8ff7a1d5d0806a6468703bbc https://doi.org/10.1109/jssc.2013.2258815 Zobrazit plný text záznamu