| Autor: |
Sigang Ryu, Jaeha Kim, Hwanseok Yeo, Yoontaek Lee, Seuk Son |
| Rok vydání: |
2013 |
| Předmět: |
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| Zdroj: |
CICC |
| DOI: |
10.1109/cicc.2013.6658470 |
| Popis: |
This paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is the PLL's second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response and achieves fast settling. Unlike the previously-reported peaking-free PLLs the proposed PLL implements the peaking-free loop filter directly in digital domain without requiring additional components. A time-to-digital converter (TDC) is implemented as a set of three binary phase-frequency detectors that oversample the timing error with time-varying offsets achieving a linear TDC gain and PLL bandwidth insensitive to the jitter condition. And a 9.2-GHz digitally-controlled LC oscillator (DCO) with transformer-based tuning realizes a predictable DCO gain set by a ratio between two digitally-controlled currents. The prototype 9.2-GHz-output digital PLL fabricated in a 65nm CMOS demonstrates a fast settling time of 1.58-μs with 690-kHz bandwidth. The PLL has a 3.477-psrms divided clock jitter and -120dBc/Hz phase noise at 10MHz offset while dissipating 63.9-mW at a 1.2-V supply. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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