The R2-D2 toolchain — Automated porting of safety-critical applications to FPGAs
| Autor: | Marc Reichenbach, Ulrich Margull, Steffen Vaas, Dietmar Fey |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Hardware architecture
business.industry Computer science 020208 electrical & electronic engineering 02 engineering and technology Porting Toolchain 020202 computer hardware & architecture Metadata AUTOSAR Data exchange Embedded system 0202 electrical engineering electronic engineering information engineering Single-core business Field-programmable gate array |
| Zdroj: | ReConFig |
| DOI: | 10.1109/reconfig.2016.7857192 |
| Popis: | Safety-critical applications require reliable hardware platforms with deterministic behavior. Concerning the increasing demand for performance, current single core solutions are not sufficient anymore. Classical multi-core processors are designed for a general application case, which provide much performance at the expense of determinism and reliability. In safety-critical applications, all required tasks are already known at development time. They are specified by a system description, like AUTOSAR. Thus, a hardware architecture providing one core for each task and one physical link for each data exchange between different tasks can be derived. However, such a highly application-specific architecture is not available. Latest FPGA technologies provide now enough resources to integrate several soft-core processors in one low-cost chip. Furthermore, the cores and their connections can be arranged flexibly in an FPGA. To bridge the gap between safety-critical applications and FPGAs, this approach provides a toolchain as addition to existing AUTOSAR design tools for automatically generating a specific hardware architecture from metadata of an AUTOSAR description. By reducing the complexity of the hardware platform drastically, a reconfigurable, reliable, deterministic, distributed (R2-D2) hardware architecture can be created. The results show that safety-critical tasks can be executed deterministically on one chip in parallel and multiple applications can be mapped to one low-cost FPGA. Furthermore, the latency of the system could be reduced extensively, so new application areas can be accessed. |
| Databáze: | OpenAIRE |
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