| Popis: |
We present the analysis and design of a FIR filter with balanced ternary coefficients (i.e., −1, 0, +1) suitable for FPGA implementation. The ternary filter taps were generated using a ΣδM process in MATLAB® and the filter implemented in VHDL. An efficient fast adder structure accumulates the partial multiplication products. Two alternative implementations in 2's complement and redundant binary signed digit representations are compared on a range of commercial FPGA devices for both pipelined and non-pipelined organizations. Using a high performance device, the filter can operate at clock rates of more than 400MHz. |
