A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead

Autor:	Shaolei Quan, Cheong Kun, Andrew J. Mason
Rok vydání:	2004
Předmět:	Logic synthesis Computer science law Logic gate Encoding (memory) Transistor Process (computing) Parallel computing Look-ahead Encoder Power (physics) law.invention
Zdroj:	ISCAS (2)
DOI:	10.1109/iscas.2004.1329381
Popis:	A power-optimized 8-bit priority encoder cell that simplifies the conventional circuit from 102 to 62 transistors is presented. A parallel priority look-ahead architecture that reduces the delay time of priority propagation is introduced. The 8-bit PE cell and parallel priority look-ahead architecture are applied to the design of a 64-bit PE in a latch-based two-stage pipelined structure. Simulation results shows that the 64-bit PE is 27% faster and 53% more power efficient than the conventional design using the same process technology.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::dae1c774c550a78bfd01e313b897e17d https://doi.org/10.1109/iscas.2004.1329381 Zobrazit plný text záznamu