A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL

Autor:	Woonyun Kim, Jaehyouk Choi, Kyutae Lim
Rok vydání:	2012
Předmět:	Engineering business.industry Phase-locked loop Voltage-controlled oscillator CMOS Hardware_GENERAL Hardware and Architecture Harmonics Hardware_INTEGRATEDCIRCUITS Charge pump Harmonic Electronic engineering Spur Electrical and Electronic Engineering business Phase frequency detector Software
Zdroj:	IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:969-973
ISSN:	1557-9999 1063-8210
DOI:	10.1109/tvlsi.2011.2129602
Popis:	This paper proposes a new reference-spur elimination architecture for a charge-pump-based phase locked loop (PLL) using an edge interpolation technique. By utilizing a charge-distribution mechanism on the control voltage of the voltage-controlled oscillator, the proposed architecture is capable of suppressing high-order harmonics of the reference spur, as well as a fundamental spur. In implementation, the eight-stage edge interpolator achieved more than 16-dB additional spur suppression. In addition, the harmonics of the reference spur within a 104-MHz frequency offset, the location of the eighth harmonic of the reference spur, were dramatically suppressed. The prototype PLL was fully integrated in a 0.18-μm CMOS technology, which occupies a 670 μm × 640 μm active chip area. Additional circuits for the edge interpolator consumes less than one-fifth of the total area and power.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::dac45e08f765c94d80e806f04dfd227f https://doi.org/10.1109/tvlsi.2011.2129602 Zobrazit plný text záznamu