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This paper deals with the design and analysis of high speed SRAM memory using ATD (Address Transition Detector) technique in 130 nm with the capacitive load of the memory is 5pF, focusing on optimizing power and delay. Reconfigurable computing is a new paradigm for current high performance computing, which promises an intermediate trade‐off between Application Specific Integrated Circuits (ASICs) and general purpose microprocessors. In modern reconfigurable computing, design space exploration of memory architecture is an important issue, which heavily influences the performance of application algorithms. One of the key components to such designs is high speed SRAM which is implemented using ATD technique. |
