Low Power Novel 10T SRAM with Stabled Optimized Area
| Autor: | Satyendra N. Biswas, Riazul Islam, Kazi Fatima Sharif |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES Computer science 020208 electrical & electronic engineering Sram cell Transistor 02 engineering and technology 01 natural sciences Power (physics) law.invention Memory cell Power consumption law 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering Static noise margin Static random-access memory |
| Zdroj: | 2018 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE). |
| DOI: | 10.1109/wiecon-ece.2018.8783036 |
| Popis: | The high demand for memory devices by decreasing power consumption is significant. SRAM has been under its renewal phase by enduring the ever-increasing delay along with supporting low power applications. A New 10 transistor (lOT) SRAM cell architecture has been proposed as explanations for the limitations of conventional SRAM models, in this paper. The proposed cell excels, in particular, three aspects: 1) data overwriting, 2) low power consumption, and 3) Improved area. The second value makes it particularly appropriate for a SRAM is stability. We have simulated and validated its performance by using 45nm predictive technology model (PTM). |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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