A family of CMOS latches with 3 stable operating points
| Autor: | Xiaoqiang Shou, Michael M. Green |
|---|---|
| Rok vydání: | 2002 |
| Předmět: |
Diode–transistor logic
Pass transistor logic AND-OR-Invert Computer science Depletion-load NMOS logic Logic simulation Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention PMOS logic Hardware_GENERAL law MOSFET Hardware_INTEGRATEDCIRCUITS Electronic engineering Pull-up resistor Logic optimization Logic probe Adiabatic circuit Digital electronics business.industry Transistor Logic family Diode-or circuit Logic level Emitter-coupled logic Resistor–transistor logic Integrated injection logic CMOS Logic gate Inverter Resistor Cmos process business Hardware_LOGICDESIGN Asynchronous circuit Voltage |
| Zdroj: | ISCAS (1) |
| DOI: | 10.1109/iscas.2001.921800 |
| Popis: | A new MOSFET latch that possesses three stable operating points is presented. This circuit is the first of its kind that can be fabricated in a standard digital CMOS process with a single supply voltage and differs from a conventional CMOS latch only by the addition of 2 resistors or 2 transistors. An open loop analysis of the new circuit is introduced to examine its performance. Four variations of this circuit are presented. It is shown that this circuit lends itself well for integrated circuit realization of multi-state logic and memory. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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