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The Quality-of-Service-Network-on-Chip (QNoC) architecture is used in complex System-on-Chip (Soc) for intercommunication. For high efficiency and throughput, Buffer Virtual-Channel (VC) input port NoC is utilized. In order to provide a good Quality-of-Service (QoS), input port buffer area optimization is important. Compared to traditional VC approaches, the current efficient dynamic VC (EDVC) organizes the buffers in an effective way to minimize area overhead for enhanced performance. In this paper, we propose an Isochronous Efficient Dynamic Virtual Channel (IEDVC) router architecture that aims to effectively organize the VC input port, prioritise packets, and provide good communication. To enhance the QoS, techniques such as frequency boosting and error termination have been introduced. Thus, with all modifications, the results of IEDVC showed that it utilizes the 14.19 % less hardware, with a 3.7% and 3.8% increase in frequency and throughput respectively. |
