An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors
| Autor: | Hiroshi Okano, S. Satoh, Yasumoto Tomita, Hitoshi Sakurai, Ryuichi Nishiyama, Tetsutaro Hashimoto, Yasushi Kakimura, Shinichiro Shirota, Yukihito Kawabe, Hideo Yamashita, Kunihiko Tajiri, Michiharu Hara |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Multi-core processor Computer science Quantization (signal processing) 020208 electrical & electronic engineering Latency (audio) Operating frequency Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Chip 01 natural sciences Line (electrical engineering) Phase-locked loop 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Voltage droop Electrical and Electronic Engineering Multipath propagation |
| Zdroj: | IEEE Journal of Solid-State Circuits. 53:1028-1037 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2017.2777101 |
| Popis: | On-die supply-voltage droops attributed to workload variations degrade the performance of high-performance microprocessors. An adaptive-clocking-control circuit was implemented for mitigating the adverse impact of supply-voltage droops on processor performance. One of the most critical requirements for adaptive-clocking supply-droop mitigation is that clock-frequency adaptation is fast enough to respond to such supply droops. To shorten the clock-frequency-adaptation latency, therefore, the adaptive-clocking-control circuit features the following schemes: the time-to-digital converter (TDC) based on multipath delay line (multipath TDC), thermometer-code-based data-processing logic, and phase-locked loop (PLL) including a direct frequency-reduction mechanism. The multipath TDC reduces quantization errors in droop detection to shorten detection-response latency. The thermometer-code-based logic does not cost extra clock cycles compared with binary-code-based logic. The direct frequency-reduction mechanism enables a PLL to quickly react to clock-modulation instruction without any intervals. These schemes contribute to faster clock-frequency-adaptation response to supply droops. A test chip including the adaptive-clocking-control circuit with SPARC processor cores was fabricated in a 20-nm CMOS process. Experimental measurements indicate that the adaptive-clocking-control circuit achieved a state-of-the-art frequency gain of 7.5%, resulting in an operating frequency as high as 5 GHz. |
| Databáze: | OpenAIRE |
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