Wafer-level packaging for harsh environment application

Autor:	C. Jia, J. Bardong, C. Gruber, A. Kenda, M. Kraft
Rok vydání:	2014
Předmět:	Die preparation Materials science business.industry Wafer bonding Electrical engineering Optoelectronics Wafer dicing business Probe card Wafer backgrinding Wafer-level packaging Die (integrated circuit) Embedded Wafer Level Ball Grid Array
Zdroj:	2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D).
DOI:	10.1109/ltb-3d.2014.6886178
Popis:	A wafer-level chip-scale packaging scheme that can withstand temperatures of 600°C and above in long-term operation is proposed. The package comprises a SOI case and a cap wafer. In the device layer of the SOI wafer, flexible springs are formed to fix target chips inside the case, so that the influence of thermal stress can be minimized. The two components are joined together through wafer bonding process under vacuum condition. Electric connection is established through Pt metallized via in SOI. Initial test results confirm the feasibility of the method.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d8e95733c322a4970587a81cf88a3ba0 https://doi.org/10.1109/ltb-3d.2014.6886178 Zobrazit plný text záznamu