Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications
| Autor: | H.-J. Cho, H.S. Oh, K.J. Nam, Y.H. Kim, K.H. Yeo, W.D. Kim, Y.S. Chung, Y.S. Nam, S.M. Kim, W.H. Kwon, M.J. Kang, I.R. Kim, H. Fukutome, C.W. Jeong, H.J. Shin, Y.S. Kim, D.W. Kim, S.H. Park, J.H. Jeong, S.B. Kim, D.W. Ha, J.H. Park, H.S. Rhee, S.J. Hyun, D.S. Shin, D.H. Kim, H.Y. Kim, S. Maeda, K.H. Lee, M.C. Kim, Y.S. Koh, B. Yoon, K. Shin, N.I. Lee, S.B. Kangh, K.H. Hwang, J.H. Lee, J.-H. Ku, S.W. Nam, S.M. Jung, H.K. Kang, J.S. Yoon, E.S. Jung |
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| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Materials science business.industry Contact resistance Doping Gate stack Electrical engineering 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Fin (extended surface) Power (physics) 0103 physical sciences Optoelectronics Node (circuits) Static random-access memory 0210 nano-technology business |
| Zdroj: | 2016 IEEE Symposium on VLSI Technology. |
| DOI: | 10.1109/vlsit.2016.7573359 |
| Popis: | 10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated. |
| Databáze: | OpenAIRE |
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