| Popis: |
Managing DRAM power and main memory energy efficiency are a prime area of concern today. There have been several methods of achieving this evolved over time. In this paper, we have explored the memory rank-power controls in a performance simulation environment. There are two distinctive, but related goals achieved out of the proposed pre-to-post silicon correlation methodology. In the first part, we focus on identifying an ideal power mode in the pre-silicon environment, with a goal of achieving maximum memory performance and minimal DRAM power consumption. In the second part, the pre-silicon results are compared with the post-silicon hardware results and a tight correlation is ensured to gain confidence on the overall methodology. In order to achieve this objective, we have identified a memory intensive DAXPY workload, to be tested in the pre-silicon simulation environment. The performance verification environment includes configuration files and behavioral VHDL models of the memory controller, to parallel a real-world memory intensive traffic. This methodology could also be extended to performance calculation of the entire system stack. |
