| Autor: |
Chanemougame Daniel, Jonathan Cobb, Chia-Tung Ho, Lars W. Liebmann, Jeffrey Smith, Victor Moroz, Pete Churchill |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
Design-Process-Technology Co-optimization for Manufacturability XIV. |
| DOI: |
10.1117/12.2554025 |
| Popis: |
An efficient Pathfinding DTCO analysis flow which allows rapid block-level power, performance, and area (PPA) characterization is presented. To optimize this flow for the exploration of innovative technology-architecture definitions, i.e. new devices and their integration into functional logic cells, the time consuming task of generating and validating a process design kit (PDK) for each technology definition is eliminated by taking advantage of automated standard cell generation and direct emulation-based parasitic extraction. Further efficiency gains are obtained through a customized flow that allows a large number of place and route (PnR) experiments to be executed automatically. The efficiency of the presented Pathfinding DTCO flow is demonstrated in experiments quantifying block-level PPA changes in different implementations of finFET and CFET devices. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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