LUT-Based Optimization For ASIC Design Flow
| Autor: | Felipe S. Marranghello, Luca Amaru, Jiong Luo, Patrick Vuillod, Vinicius N. Possani, Alan Mishchenko, Giovanni De Micheli, Eleonora Testa, Christopher Casares |
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| Rok vydání: | 2021 |
| Předmět: |
Computer science
Integrated circuit law.invention Computer architecture Application-specific integrated circuit law Logic gate Lookup table Hardware_INTEGRATEDCIRCUITS Table (database) Node (circuits) Electronic design automation Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Hardware_LOGICDESIGN |
| Zdroj: | DAC |
| DOI: | 10.1109/dac18074.2021.9586132 |
| Popis: | Look-up Table (LUT) mapping and optimization is an important step in Field Programmable Gate Arrays (FPGAs) design. The effectiveness of LUT synthesis improved dramatically in the last decades, thanks to optimization and mapping innovations naturally tailored for FPGAs. In this paper, we develop a new LUT-based optimization flow that is tailored for the synthesis of Application-Specific Integrated Circuits (ASICs) rather than FPGAs. We enhance LUT mapping to consider the literal/AIG cost of LUT nodes. We extend traditional Boolean methods to simplify and re-shape LUT-networks, targeting the best AIG/mapped-network implementation, after decomposition. Intuitively, literal-driven LUT packing behaves as a powerful fanin-bound node elimination, unveiling higher-order Boolean simplification opportunities. We embed our proposed LUT-based optimization flow, area oriented, in a commercial synthesis tool. Using our methodology, we improve 12 of the best area results in the EPFL synthesis competition. Employed in a commercial EDA flow for ASICs, our LUT optimization reduces area by 1.80%, total negative slack by 0.39%, and switching power by 1.72%, after physical implementation, at 5% runtime cost. |
| Databáze: | OpenAIRE |
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