A Logic-compatible Embedded DRAM Utilizing Common-body Toggled Capacitive Cross-talk
| Autor: | Yeonbae Chung, Hritom Das, Weijie Cheng |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Engineering Sense amplifier business.industry 020208 electrical & electronic engineering 02 engineering and technology eDRAM Chip 01 natural sciences Electronic Optical and Magnetic Materials CMOS 0103 physical sciences Computer data storage 0202 electrical engineering electronic engineering information engineering Electronic engineering Node (circuits) Electrical and Electronic Engineering Data retention business Dram |
| Zdroj: | JSTS:Journal of Semiconductor Technology and Science. 16:781-792 |
| ISSN: | 1598-1657 |
| Popis: | This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures 600 μs at 1.1 V and 85℃, enhancing by 87.5% over the conventional design approach. |
| Databáze: | OpenAIRE |
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