A Compressed Sensing Analog-to-Information Converter With Edge-Triggered SAR ADC Core

Autor:	Robert D'Angelo, Shuchin Aeron, Michael Trakimas, Sameer Sonkusale, T.M. Hancock
Rok vydání:	2013
Předmět:	Effective number of bits Compressed sensing CMOS Computer science Bandwidth (signal processing) Hardware_INTEGRATEDCIRCUITS Electronic engineering Nyquist–Shannon sampling theorem Figure of merit Successive approximation ADC Clock generator Electrical and Electronic Engineering
Zdroj:	IEEE Transactions on Circuits and Systems I: Regular Papers. 60:1135-1148
ISSN:	1558-0806 1549-8328
Popis:	This paper presents the design and implementation of an analog-to-information converter (AIC) capable of Nyquist and compressed sensing modes of operation. The core of the AIC is a 10-bit edge-triggered charge-sharing SAR ADC with a figure of merit (FOM) of 55 fJ/conversion-step and Nyquist-sampling rate of 9.5 Msample/s. The integration of a pseudorandom clock generator enables compressed sensing operation via random sampling and subsequent asynchronous successive approximation conversion by the core ADC. The AIC allows complete reconstruction of a spectrum consisting of sparse single tones or sparse frequency bands using compressed sensing algorithms based on l1-minimization as well as l1,2 regularization, which exploits group sparsity. Implemented in 90 nm CMOS, the prototype SAR ADC core achieves a maximum sample rate of 9.5 MS/s, an ENOB of 9.3 bits, and consumes 550 μW from a 1.2 V supply. Measurement results of the AIC demonstrate an effective bandwidth of 25 MHz, which is 5 × greater than Nyquist-sampling rate with an improved effective FOM of 12.2 fJ/conversion-step for signals with sparse frequency support.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d699b64891b50976f840023d6972476a https://doi.org/10.1109/tcsi.2013.2244435 Zobrazit plný text záznamu