| Autor: |
Kim Cheheung, Kang Hyunwook, Hong Hyeokki |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
ISCAS |
| DOI: |
10.1109/iscas45731.2020.9180991 |
| Popis: |
This paper presents a power and area efficient architecture for the Internet of Things (IoT) and biomedical sensor read-out applications. The architecture adopts step-wise charging to support voltage stacking power delivery solution for digital processors. MSB floating decision scheme with bottom-plate sampling is adopted for low power and reduced decision error. The errors from floating decision scheme and DAC settling are corrected through binary-sum based non-binary decision error correction scheme. The prototype 12b ADC fabricated in a 55nm CMOS process operates at a sampling rate of 10MS/s under 0.9V supply while maintaining an ENOB higher than 10b up to the Nyquist frequency of the input signal with a power consumption of 40.2μW. It shows a state-of-the-art FoM of 3.85fJ/conversion-step without a complex calibration scheme compared to prior-art. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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