The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks
Autor: | James D. Meindl, D.C. Sekar |
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Rok vydání: | 2007 |
Předmět: | |
Zdroj: | 2007 IEEE International Interconnect Technology Conferencee. |
DOI: | 10.1109/iitc.2007.382371 |
Popis: | This paper studies the impact of multi-core architectures on design of chip-level interconnect networks. A dual core 3 GHz processor is found to require 23% fewer metal levels than a single core 6 GHz processor while a quad core 1.5 GHz processor needs 38% fewer interconnect levels than the single core 6 GHz processor. This is because lower frequency chips can use smaller pitch wires and pack the wiring into a fewer number of metal levels. |
Databáze: | OpenAIRE |
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