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We present a novel asynchronous RSFQ digital circuit, Test-Timed RSFQ digital circuit and system(TT), in this paper. With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the overhead of global clock distribution and the timing uncertainty. According to the scheme, the timing signal of the logic module is generated by a test logic module. The delay module can be removed from our circuit which should be used in previous asynchronous circuits. Finally, the simulation results for the Test-Timed data processing pipeline based on TT scheme are presented. |
