| Autor: |
T. Fukase, H. Nakamura, I. Yamamoto, Kazuya Uejima, N. Kimizuka, Toru Tatsumi, Toshiyuki Iwamoto, T. Nakayama, Kiyotaka Imai, Y. Nakahara, K. Taniguchi, T. Abe, K. Masuzaki |
| Rok vydání: |
2006 |
| Předmět: |
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| Zdroj: |
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.. |
| DOI: |
10.1109/vlsit.2006.1705265 |
| Popis: |
A 55nm node low standby power/generic CMOS technology is demonstrated. The transistor deploys the combination of high-k gate dielectric film and process-induced stress technologies. It features high drive currents with low leakage, wide coverage of transistor performance and process simplicity. Ion of 525/295 muA/mum at Ion of 20 muA/mum and Ion of 780/400 muA/mum at Ioff of 3 nA/mum with supply voltage of 1.2 V have been achieved. A leading-edge ArF immersion lithography has been utilized for fine-pitch design rules such as L/S of 160 nm for metal 1 layer. A 0.432 mum2 SRAM cell shows a sufficient SNM of 130 mV at supply voltage of 0.8 V |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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