Design and development of 130-nanometer ICs for a multi-Gigabit switching network system

Autor:	C. Joly, Demin Wang, F. Chiu, P. Tran, S. Riley, S. Yang, D. Le, H. Truong, K. Ruparel, S. Nguyen, J. Gill, V. Chagarlamudi, X. Zhong, V. Jayapal, C. Yang, M. Cheung, Min Li, Trung-Viet Nguyen, I. Ahmed, N. Burnside, A. Khan, A. Tsou, D. Ge, J. Yu, Y. Fan, P. McKeever, V. Ghanta, Oanh Kim, J. Zhang, H. Mak, P. Huang, K. Rajan
Rok vydání:	2004
Předmět:	Engineering business.industry Network packet Transistor Integrated circuit design Integrated circuit law.invention Packet switching CMOS Hardware_GENERAL law Gigabit Hardware_INTEGRATEDCIRCUITS Electronic engineering Physical design business
Zdroj:	CICC
DOI:	10.1109/cicc.2004.1358809
Popis:	A system-centric, fully-hierarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-Gigabit switching network system, are presented. The system is capable of switching more than 500 million packets per second. Electrical and physical design methods for one IC are described. /spl sim/76 M transistors are integrated in a 130 nm CMOS 8-metal process. Functional and electrical design requirements were achieved with the first silicon.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d59e673c46eaa441196d1b98562f1d60 https://doi.org/10.1109/cicc.2004.1358809 Zobrazit plný text záznamu