Poly-Si gate patterning issues for ultimate MOSFET
| Autor: | S. Renard, M. Heitzmann, A.M. Papon, Didier Louis, M.E. Nier, C. Fery |
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| Rok vydání: | 2002 |
| Předmět: |
Encountered problems
Materials science Gate length Nanotechnology Hardware_PERFORMANCEANDRELIABILITY Condensed Matter Physics Engraving Polysilicon gate Engineering physics Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials CMOS Etching (microfabrication) visual_art MOSFET Hardware_INTEGRATEDCIRCUITS visual_art.visual_art_medium Electrical and Electronic Engineering Critical dimension Hardware_LOGICDESIGN |
| Zdroj: | Microelectronic Engineering. :859-865 |
| ISSN: | 0167-9317 |
| Popis: | The current challenges of developing an etching process for the patterning of MOSFET gates with critical dimensions below 30 nm has been tackled by various independent R&D groups world-wide. This paper discusses the commonly encountered problems for etching of critical gate length and examines strategies to successfully pattern a sub-50 nm polysilicon gate for an ultimate CMOS technology. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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