A sequential circuit structure with combinational test generation complexity and its application
Autor: | Tomoya Takasaki, Hideo Fujiwara, Satoshi Ohtake |
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Rok vydání: | 1997 |
Předmět: |
Combinational logic
Sequential logic Finite-state machine Computational complexity theory Integrated circuit Automatic test pattern generation Topology Theoretical Computer Science law.invention Computational Theory and Mathematics Hardware and Architecture law Realization (systems) Algorithm Testability Hardware_LOGICDESIGN Information Systems Mathematics |
Zdroj: | Systems and Computers in Japan. 28:11-21 |
ISSN: | 1520-684X 0882-1666 |
DOI: | 10.1002/(sici)1520-684x(199710)28:11<11::aid-scj2>3.0.co;2-n |
Popis: | If, upon substituting signal lines for all flip-flops in a sequential circuit, the test generation problem for this sequential circuit can be reduced to the problem of test generation for a combinational circuit, one may call this sequential circuit a sequential circuit allowing test generation with combinational test generation complexity. For example, balanced structures are characterized by this feature. The authors introduce a new wider class called internally balanced structures. The sequential circuits can be classified by the circuit structure as follows: {sequential circuits of acyclic structure} ⊃ {sequential circuits of internally balanced structure} ⊃ {sequential circuits of balanced structure}. It is shown that, as opposed to sequential circuits of acyclic structure, which do not necessarily allow test generations with combinational test generation complexity, sequential circuits of internally balanced structure and balanced structure allow test generation with combinational test generation complexity. On the other hand, it is shown that finite state machines (FSM) can be grouped by their realization possibility as follows: {FSM allowing realization as acyclic structure} = {FSM allowing realization as internally balanced structure} ⊃ {FSM allowing realization as balanced structure}. Finally, the authors discuss using features of the internally balanced structures which allow test generation with combinational test generation complexity for implementing designs for testability based on the new partial scan approach, and for reducing the test generation time in sequential circuits. |
Databáze: | OpenAIRE |
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