Autor: |
Dorleta Cortaberria Sanz, Gilles Metellus, Francois Guyader, Dave Thomas, Yiping Song, Keith Buchanan, Alain Inard, Tony Wilby, Jean Michailos, N. Hotellier |
Rok vydání: |
2010 |
Předmět: |
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Zdroj: |
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2010:000539-000556 |
ISSN: |
2380-4491 |
DOI: |
10.4071/2010dpc-ta14 |
Popis: |
One of the first device types to benefit from TSV implementation is the CMOS image sensor, an image capture device designed to combine high image quality within a compact form-factor that can be mass produced at low cost. End markets include mobile phones, PDAs and gaming consoles. STMicroelectronics is pioneering their production, based on ≤65nm CMOS technology, at its 300mm facility in Crolles. These sensors employ TSVs as part of a wafer level package allowing the camera module to be directly soldered to a phone PCB thereby saving cost, space and time to manufacture. SPTS's Versalis fxP system is being used to combine multiple TSV formation processes onto one platform including hard-mask deposition, hard-mask etching, TSV etching, partial PMD etching, dielectric liner deposition and spacer etching to define the area for the metal contact. All processes are carried out on a silicon wafer bonded to a glass carrier, through which the final device is illuminated. We will present a TSV silicon etch process for 70 μm x 70 μm Vias in a thinned 300mm silicon wafer on glass carriers with an etch rate uniformity of ≤±1% and sidewall scalloping in the range 80–210 nm. We will show that this process can be conveniently mixed in production with the various oxide etches. A PECVD dielectric liner deposited at 8 MVcm−1 and leakage current Furthermore the successful implementation of TSV technology on ST's CMOS image sensors will be demonstrated through a combination of electrical characteristics, parametric device data and overall device performance/reliability. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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