Towards design and automation of a scalable split-radix FFT processor for high throughput applications
| Autor: | Shahid Masud, Adnan Rauf, Muhammad Adeel Pasha |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Signal processing
Computer Networks and Communications business.industry Computer science 020208 electrical & electronic engineering Fast Fourier transform 02 engineering and technology Automation 020202 computer hardware & architecture Application-specific integrated circuit Artificial Intelligence Hardware and Architecture Scalability VHDL 0202 electrical engineering electronic engineering information engineering Radix Field-programmable gate array business computer Software Computer hardware computer.programming_language |
| Zdroj: | Microprocessors and Microsystems. 65:148-157 |
| ISSN: | 0141-9331 |
| DOI: | 10.1016/j.micpro.2018.12.008 |
| Popis: | Fast Fourier Transform (FFT) is a rudimentary operation in signal processing. Modern high speed signal processing and communications standards, such as 4G LTE, 5G, Internet of Things (IoT), etc., necessitate a high throughput implementation of FFT. Moreover the FFT resolution required in aforementioned standards tends to vary with the operation mode. It is, therefore, highly desirable to have a FFT implementation that not only meets the high throughput demand but is also scalable to cater any selectable N-point FFT resolution. In this paper, our contribution is two-fold. First, we have analyzed in details the operational latency and mathematical consistency of our proposed split-radix 4/8 FFT algorithm which is comparable in latency with radix-8 algorithm but is considerably less complex for large-size FFTs. Second, we have developed a JAVA-based automation tool that generates high level implementation details and VHDL descriptions of an adaptive N-point split-radix 4/8 FFT processor. The resulting design can then be rapidly prototyped and synthesized on different hardware platforms like Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Experimental results show that our proposed auto-generated modular design is comparable in resource usage with the hand-crafted fixed-size designs reported in the literature while providing considerable reduction in design effort and time. |
| Databáze: | OpenAIRE |
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