FPGA realization of low power multi-layer perceptron full adder to minimize EDP of modular multiplier

Autor:	Pakkiraiah C, R V S. Satyanarayana
Rok vydání:	2021
Zdroj:	International Journal of Electronics Engineering and Applications. 10:01-12
ISSN:	2321-3477
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::d4d32ceb6453eaaef868f4e5f4a512a1 https://doi.org/10.30696/ijeea.x.ii.2022.01-12 Zobrazit plný text záznamu