FPGA realization of low power multi-layer perceptron full adder to minimize EDP of modular multiplier
| Autor: | Pakkiraiah C, R V S. Satyanarayana |
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| Rok vydání: | 2021 |
| Zdroj: | International Journal of Electronics Engineering and Applications. 10:01-12 |
| ISSN: | 2321-3477 |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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