Asymmetrically reliable caches for multicore architectures under performance and energy constraints
| Autor: | Sanem Arslan, Oguz Tosun, Mahmut Kandemir, Haluk Rahmi Topcuoglu |
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| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Multi-core processor Hardware_MEMORYSTRUCTURES Computer Networks and Communications business.industry Computer science Multiprocessing 02 engineering and technology Energy consumption 01 natural sciences 020202 computer hardware & architecture Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Overhead (computing) Cache business Software Reliability (statistics) Parity bit |
| Zdroj: | Cluster Computing. 19:1819-1833 |
| ISSN: | 1573-7543 1386-7857 |
| DOI: | 10.1007/s10586-016-0641-2 |
| Popis: | Cache structures in a multicore system are more vulnerable to soft errors due to high transistor density. Protecting all caches unselectively has notable overhead on performance and energy consumption. In this study, we propose asymmetrically reliable caches to supply reliability need of the system using sufficient additional hardware under the performance and energy constraints. In our framework, a chip multiprocessor is composed of a high reliability core which has ECC protection, and a set of low reliability cores which have no protection on their data caches. Between two types of cores, there is also a middle-level reliability core which has only parity check. Application threads are mapped on the different cores in terms of reliability based on their critical data usage. The experimental results for selected applications show that our proposed techniques improve reliability with considerable performance and energy overhead on the average compared to traditional unsafe caches. |
| Databáze: | OpenAIRE |
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